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KAD2708C
Data Sheet December 5, 2008 FN6812.0
8-Bit, 275/210/170/105MSPS A/D Converter
The KAD2708C is the industry's lowest power, 8-bit, 275MSPS, high performance Analog-to-Digital converter. It is designed with Intersil's proprietary FemtoChargeTM technology on a standard CMOS process. The KAD2708C offers high dynamic performance (49.2dBFS SNR @ fIN = 138MHz) while consuming less than 265mW. Features include an over-range indicator and a selectable divide-by-2 input clock divider. The KAD2708C is one member of a pin-compatible family offering 8 and 10-bit ADCs with sample rates from 105MSPS to 350MSPS and LVCMOS or LVDS-compatible outputs (Table 1). This family of products is available in 68-pin RoHS-compliant QFN packages with exposed paddle. Performance is specified over the full industrial temperature range (-40C to +85C).
AVDD3 CLKDIV AVDD2 OVDD
Features
* On-Chip Reference * Internal Track and Hold * 1.5VP-P Differential Input Voltage * 600MHz Analog Input Bandwidth * Two's Complement or Binary Output * Over-Range Indicator * Selectable /2 Clock Input * LVCMOS Outputs
Applications
* High-Performance Data Acquisition * Portable Oscilloscope * Medical Imaging * Cable Head Ends * Power-Amplifier Linearization
CLK_P CLK_N
Clock Generation
CLKOUT
* Radar and Satellite Antenna Array Processing * Broadband Communications
D7 - D0
* Point-to-Point Microwave Systems * Communications Test Equipment
INP
S/H
INN VREF VREFSEL VCM
8-bit 275MSPS ADC
+ -
8
LVCMOS Drivers
OR
Key Specifications
2SC
1.21 V
* SNR of 49.2dBFS at fS = 275MSPS, fIN = 138MHz * SFDR of 66.6dBc at fS = 275MSPS, fIN = 138MHz * Power Consumption 265mW at fS = 275MSPS
OVSS
AVSS
Pin-Compatible Family
TABLE 1. PIN-COMPATIBLE PRODUCTS RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS PKG. DWG. # 8 Bits 350MSPS 10 Bits 275MSPS 8 Bits 275MSPS 10 Bits 210MSPS 8 Bits 210MSPS 10 Bits 170MSPS 8 Bits 170MSPS 10 Bits 105MSPS 8 Bits 105MSPS KAD2708L-35 KAD2710L-27 KAD2708L-27 KAD2710L-21 KAD2708L-21 KAD2710L-17 KAD2708L-17 KAD2710L-10 KAD2708L-10 KAD2710C-27 KAD2708C-27 KAD2710C-21 KAD2708C-21 KAD2710C-17 KAD2708C-17 KAD2710C-10 KAD2708C-10
Ordering Information
PART NUMBER KAD2708C-27Q68 KAD2708C-21Q68 KAD2708C-17Q68 KAD2708C-10Q68 SPEED (MSPS) 275 210 170 105 TEMP. RANGE (C) PACKAGE
-40 to +85 68 Ld QFN L68.10x10B -40 to +85 68 Ld QFN L68.10x10B -40 to +85 68 Ld QFN L68.10x10B -40 to +85 68 Ld QFN L68.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
KAD2708C Table of Contents
Absolute Maximum Ratings ......................................... 3 Thermal Information...................................................... 3 Electrical Specifications ............................................... 3 Digital Specifications .................................................... 4 Timing Diagram ............................................................. 5 Timing Specifications ................................................... 5 Thermal Impedance....................................................... 5 ESD ................................................................................. 5 Pin Description .............................................................. 6 Pin Configuration .......................................................... 7 Typical Performance Curves ........................................ 8 Functional Description ................................................. 11 Reset .......................................................................... Voltage Reference...................................................... Analog Input ............................................................... Clock Input ................................................................. Jitter............................................................................ Digital Outputs ............................................................ 11 11 11 12 12 13
Equivalent Circuits........................................................ 13 Layout Considerations ................................................. 14 Split Ground and Power Planes ................................. Clock Input Considerations......................................... Bypass and Filtering ................................................... LVCMOS Outputs....................................................... Unused Inputs ............................................................ 14 14 14 14 14
Definitions...................................................................... 14 Package Outline Drawing ............................................. 15 L68.10x10B ................................................................ 15
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FN6812.0 December 5, 2008
KAD2708C
Absolute Maximum Ratings
AVDD2 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVDD3 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V OVDD2 to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V Analog Inputs to AVSS. . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD2 + 0.3V Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4V to AVDD3 + 0.3V Logic Inputs to OVSS (RST, 2SC) . . . . . . . . -0.4V to OVDD2 + 0.3V VREF to AVSS . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V Analog Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Logic Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA CMOS Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Information
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), fSAMPLE = 275MSPS, 210MSPS, 170MSPS and 105MSPS, fIN = Nyquist at -0.5dBFS. KAD2708C-27 PARAMETER DC SPECIFICATIONS Analog Input Full-Scale Analog Input Range Full Scale Range Temp. Drift Common-Mode Output Voltage Power Requirements 1.8V Analog Supply Voltage 3.3V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 3.3V Analog Supply Current 1.8V Digital Supply Current Power Dissipation AC SPECIFICATIONS Maximum Conversion Rate Minimum Conversion Rate Differential Nonlinearity Integral Nonlinearity Signal-to-Noise Ratio fS MAX fS MIN DNL INL SNR fIN = 10MHz fIN = Nyquist fIN = 430MHz 46.5 -0.3 -0.8 0.2 0.2 50.4 49.2 49.0 46.5 275 50 0.4 0.8 -0.3 -0.8 0.2 0.2 49.5 49.2 49.1 46.5 210 50 0.4 0.8 -0.3 -0.8 0.2 0.2 49.5 49.2 49.1 46.5 170 50 0.4 0.8 -0.3 -0.8 0.2 0.2 49.5 49.2 49.1 105 50 0.4 0.8 MSPS MSPS LSB LSB dBFS dBFS dBFS AVDD2 AVDD3 OVDD IAVDD2 IAVDD3
I OVDD
KAD2708C-21 TYP
KAD2708C-17 TYP
KAD2708C-10 TYP MAX UNITS
SYMBOL CONDITIONS MIN
TYP
MAX MIN
MAX MIN
MAX MIN
VFS AVTC VCM Full Temp
1.4
1.5 230 860
1.6
1.4
1.5 210 860
1.6
1.4
1.5 198 860
1.6
1.4
1.5 178 860
1.6
VP-P ppm/C mV
1.7 3.15 1.7
1.8 3.3 1.8 44 41 26 261
1.9
1.7
1.8 3.3 1.8 38 33 25 222
1.9
1.7
1.8 3.3 1.8 35 28 24 199
1.9
1.7
1.8 3.3 1.8 29 21 23 163
1.9 3.45 1.9 33 24 26 185
V V V mA mA mA mW
3.45 3.15 1.9 51 45 30 294 1.7
3.45 3.15 1.9 42 37 28 248 1.7
3.45 3.15 1.9 39 32 27 224 1.7
PD
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FN6812.0 December 5, 2008
KAD2708C
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), fSAMPLE = 275MSPS, 210MSPS, 170MSPS and 105MSPS, fIN = Nyquist at -0.5dBFS. (Continued) KAD2708C-27 PARAMETER Signal-to-Noise and Distortion SYMBOL CONDITIONS MIN SINAD fIN = 10MHz fIN = Nyquist fIN = 430MHz Effective Number of Bits ENOB fIN = 10MHz fIN = Nyquist fIN = 430MHz Spurious-Free Dynamic Range SFDR fIN = 10MHz fIN = Nyquist fIN = 430MHz Two-Tone SFDR Word Error Rate Full Power Bandwidth 2TSFDR fIN = 133MHz, 135MHz WER FPBW 61 7.4 46.5 TYP 49.2 49.2 48.9 7.9 7.9 7.8 67.6 66.6 66.1 63 10-12 600 61 7.4 46.5 KAD2708C-21 TYP 49.5 49.2 48.9 7.9 7.9 7.8 69.1 69.1 69.0 65 10-12 600 61 7.4 46.5 KAD2708C-17 TYP 49.5 49.2 49.0 7.9 7.9 7.8 69.1 69.1 69.0 65 10-12 600 61 7.4 46.5 KAD2708C-10 TYP 49.5 49.2 48.9 7.9 7.9 7.8 69.1 69.1 68.9 65 10-12 600 MHz MAX UNITS dBFS dBFS dBFS Bits Bits Bits dBc dBc dBc dBc
MAX MIN
MAX MIN
MAX MIN
Digital Specifications
PARAMETER INPUTS High Input Voltage (VREFSEL) Low Input Voltage (VREFSEL) Input Current High (VREFSEL) Input Current Low (VREFSEL) High Input Voltage (CLKDIV) Low Input Voltage (CLKDIV) Input Current High (CLKDIV) Input Current Low (CLKDIV) High Input Voltage (RST,2SC) Low Input Voltage (RST,2SC) Input Current High (RST,2SC) Input Current Low (RST,2SC) Input Capacitance CLKP, CLKN P-P Differential Input Voltage CLKP, CLKN Differential Input Resistance CLKP, CLKN Common-Mode Input Voltage LVCMOS OUTPUTS Voltage Output High Voltage Output Low Output Rise Time Output Fall Time VOH VOL tR tF 1.8 0 1.8 1.4 V V ns ns VREFSEL VIH VREFSEL VIL VREFSEL IIH VREFSEL IIL CLKDIV VIH CLKDIV VIL CLKDIV IIH CLKDIV IIL RST,2SC VIH RST,2SC VIL RST,2SC IIH RST,2SC IIL CDI VCDI RCDI VCCI 0.5 10 0.9 VIN = OVDD VIN = OVSS 0 25 1 50 3 3.6 VIN = AVDD3 VIN = AVSS 25 0 0.8*OVDD2 0.2*OVDD2 10 75 65 1 VIN = AVDD3 VIN = AVSS 0 25 0.8*AVDD3 0.2*AVDD3 75 10 1 65 0.8*AVDD3 0.2*AVDD3 10 75 V V A A V V A A V V A A pF VP-P M V SYMBOL CONDITIONS MIN TYP MAX UNITS
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FN6812.0 December 5, 2008
KAD2708C Timing Diagram
Sample N
INP
INN
tA
CLKN CLKP
L tPID
CLKOUT
tPCD tPH
D[7:0]
Data N-L invalid
Data N-L+1
Data N
FIGURE 1. LVCMOS TIMING DIAGRAM
Timing Specifications
PARAMETER Aperture Delay RMS Aperture Jitter Input Clock to Data Propagation Delay Data Hold Time Output Clock to Data Propagation Delay Latency (Pipeline Delay) Overvoltage Recovery SYMBOL tA jA tPID tPH tPCD L tOVR 3.5 -300 2.8 28 1 3.7 MIN TYP 1.7 200 5.0 6.5 MAX UNITS ns fs ns ps ns cycles cycle
Thermal Impedance
PARAMETER Junction to Paddle (Note 1) NOTE: 1. Paddle soldered to ground plane. SYMBOL JP TYP 30 UNIT C/W
ESD
Electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Intersil for the specific ESD sensitivity rating of this product.
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FN6812.0 December 5, 2008
KAD2708C Pin Description
PIN NUMBER 1, 14, 18, 20 2, 7, 10, 19, 21, 24 3 4 5 6, 15, 16, 25 8, 9 11-13, 29-36, 37, 39, 42, 46, 48, 50, 53, 54, 56, 58, 62, 63, 67 17 22, 23 26, 45, 61 27, 41, 44, 60 28 38 40 43 47 49 51 53 55 57 59 64-66 68 Exposed Paddle 2SC AVSS NAME AVDD2 AVSS VREF VREFSEL VCM AVDD3 INP, INN DNC CLKDIV CLKN, CLKP OVSS OVDD2 RST D0 D1 CLKOUT D2 D3 D4 D5 D6 D7 OR 1.8V Analog Supply Analog Supply Return Reference Voltage Out/In Reference Voltage Select (0:Int 1:Ext) Common-Mode Voltage Output 3.3V Analog Supply Analog Input Positive, Negative Do Not Connect Clock Divide by Two (Active Low) Clock Input Complement, True Output Supply Return 1.8V CMOS Supply Power On Reset (Active Low) LVCMOS Bit 0 (LSB) Output LVCMOS Bit 1 Output LVCMOS Clock Output LVCMOS Bit 2 Output LVCMOS Bit 3 Output LVCMOS Bit 4 Output LVCMOS Bit 5 Output LVCMOS Bit 6 Output LVCMOS Bit 7 Output Over-Range Connect to OVDD2 Two's Complement Select (Active Low) Analog Supply Return FUNCTION
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FN6812.0 December 5, 2008
KAD2708C Pin Configuration
OVDD2 OVDD2 OVDD2 OVDD2 OVSS
DNC
DNC
DNC
DNC
DNC
DNC 54
68
67
66
65
64
63
62
61
60
59
58
57
56
55
53
52
DNC
2SC
OR
D7
D6
D5
AVDD2 AVSS VREF VREFSEL VCM AVDD3 AVSS INP INN AVSS DNC DNC DNC AVDD2 AVDD3 AVDD3 CLKDIV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 49 48 47 46
D4 DNC D3 DNC D2 DNC OVSS OVDD2 CLKOUT DNC OVDD2 D1 DNC D0 DNC DNC DNC
KAD2708C
68 QFN
45 44 43 42 41 40 39 38 37 36 35
Top View Not to Scale
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 DNC
33 DNC
AVDD2
AVDD2
AVDD3
OVDD2
AVSS
AVSS
AVSS
CLKN
OVSS
CLKP
RST
DNC
DNC
DNC
FIGURE 2. PIN CONFIGURATION
7
DNC
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FN6812.0 December 5, 2008
KAD2708C Typical Performance Curves
70
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25C, fSAMPLE = 275MSPS, fIN = 137MHz, AIN = -0.5dBFS unless noted.
-50 -55
S N R( d B F S ), S FD R (dBc) (dB
65
SFDR
-60
60
(dBc) HD 2, HD3( dBc
-65 -70 -75 -80
HD3
55
50
45
SNR
-85 -90
5 105 205 305 f IN (M Hz) 405 505
HD2
40
5
10 5
205
3 05 f IN( MHz)
405
505
FIGURE 3. SNR AND SFDR vs fIN
FIGURE 4. HD2 AND HD3 vs fIN
80
-20
(dBc) S N R (d B F S ) , S F D R (d
70
-30
60
HD3
SNR
50
HD2, HD3 (dBc) dBc
-40 -50 -60 -70 -80 -30
HD2
40
SFDR
30
20 -30 -2 5 -20 -1 5 A IN ( d B F S ) -1 0 -5 0
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
FIGURE 6. HD2 AND HD3 vs AIN
FIGURE 5. SNR AND SFDR vs AIN
80 76
SFDR
-65 -70 HD2, HD3(dBc) -75
HD3
SNR(dBFS), SFDR (dBc)
72 68 64 60 56 52 48 44 40 50 100 150 200 250 f SA MP LE (fS ) (MSPS) 300 350
SNR
-80 -85
HD2
-90 50 100 150 200 250 fSAMPLE (MHz) 300 350
FIGURE 7. SNR AND SFDR vs fSAMPLE
FIGURE 8. HD2 AND HD3 vs fSAMPLE
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FN6812.0 December 5, 2008
KAD2708C Typical Performance Curves
280 260 Power Dissipation (PD) (mW) 240 220 200 180 160 140 120 100 50 100 150 200 f SAMPLE (f S) (MSPS) 250 300
-1 0 32 64 96 12 8 CODE 160 19 2 2 24 2 55 DNL (LS Bs)
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25C, fSAMPLE = 275MSPS, fIN = 137MHz, AIN = -0.5dBFS unless noted. (Continued)
1 0 .75 0.5 0 .25 0 -0 .25 -0.5 -0 .75
FIGURE 9. POWER DISSIPATION vs fSAMPLE
FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE
1 0.7 5 0.5 0.2 5 0 -0.2 5 -0.5 -0.7 5 -1 0
50,000 45,000 40,000 35,000 CODE COUNT 30,000 25,000 20,000 15,000 10,000 5,000
32 64 96 12 8 CODE 1 60 192 224 255
INL (L SBs)
0 124
125
126
127 CODE
128
129
130
FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE
0 Ain = -0.47dBFS -20 SNR = 49.4dBFS SFDR = 68.4dBc AMPLITUDE (dB) -40 SINAD = 49.3dBFS HD2 = -86dBc -60 HD3 = -69dBc AMPLITUDE (dB) -40 -20 0
FIGURE 12. NOISE HISTOGRAM
Ain = -0.47dBFS SNR = 49.4dBFS SFDR = 69.2dBc SINAD = 49.4dBFS HD2 = -81dBc -60 HD3 = -91dBc
-80
-80
-100
-100
-120 0
20
40
60 80 FREQUENCY (MHz)
100
120
-120 0
20
40
60 80 FREQUENCY (MHz)
100
120
FIGURE 13. OUTPUT SPECTRUM @ 9.865MHz
FIGURE 14. OUTPUT SPECTRUM @ 133.805MHz
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FN6812.0 December 5, 2008
KAD2708C Typical Performance Curves
0 Ain = -0.48dBFS -20 SNR = 49.3dBFS SFDR = 63dBc -40 SINAD = 49.1dBFS HD2 = -63dBc -60 HD3 = -67dBc AMPLITUDE (dB) -40 -20
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25C, fSAMPLE = 275MSPS, fIN = 137MHz, AIN = -0.5dBFS unless noted. (Continued)
0 Ain = -7.1dBFS 2TSFDR = 67dBc IMD3 = -74dBF S
AMPLITUDE (dB)
-60
-80
-80
-100
-100
-120 0
20
40
60 80 FREQUENCY (MHz)
100
120
-120
0
20
40
60 80 FREQUENCY (MHz)
100
120
FIGURE 15. OUTPUT SPECTRUM @ 299.645MHz
0
Ain = -7dBFS -20 2TSF DR = 73dBc IMD3 = -81dBFS AMPLIT UDE (dB) -40
FIGURE 16. TWO-TONE SPECTRUM @ 69MHz, 70MHz
0
Ain = -7dBFS -20 2TSFDR = 63dBc IMD3 = -76dBFS -40 AMPLITUDE (dB)
-60
-60
-80
-80
-100
-100
-120
0
20
40
60 80 FREQ UENCY (MHz)
100
120
-120 0
20
40
60 80 FREQUENCY (MHz)
100
120
FIGURE 17. TWO-TONE SPECTRUM @ 140MHz, 141MHz
FIGURE 18. TWO-TONE SPECTRUM @ 300MHz, 305MHz
800 700 600 tCAL (ms) 500 400
75 70 SNR(dBFS), SFDR(dBc) 65 60 55 50 45 40 -40 -20 0 20 40 60 AMBIENT TEMPERATURE, C 80
SNR SFDR
300 200 100
125
150
175 200 f SAMPLE (f S) (MSPS)
225
250
275
FIGURE 19. SNR AND SFDR vs TEMPERATURE
FIGURE 20. CALIBRATION TIME vs fS
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FN6812.0 December 5, 2008
KAD2708C Functional Description
The KAD2708 is an eight bit, 275MSPS A/D converter in a pipelined architecture. The input voltage is captured by a sample & hold circuit and converted to a unit of charge. Proprietary charge domain techniques are used to compare the input to a series of reference charges. These comparisons determine the digital code for each input value. The converter pipeline requires 24 sample clocks to produce a result. Digital error correction is also applied, resulting in a total latency of 28 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. At start-up, a self-calibration is performed to minimize gain and offset errors. The reset pin (RST) is initially held low internally at power-up and will remain in that state until the calibration is complete. The clock frequency should remain fixed during this time. Calibration accuracy is maintained for the sample rate at which it is performed, and therefore should be repeated if the clock frequency is changed by more than 10%. Recalibration can be initiated via the RST pin, or power cycling, at any time.
Voltage Reference
The VREF pin is the full-scale reference, which sets the full-scale input voltage for the chip and requires a bypass capacitor of 0.1F or larger. An internally generated reference voltage is provided from a bandgap voltage buffer. This buffer can sink or source up to 50A externally. An external voltage may be applied to this pin to provide a more accurate reference than the internally generated bandgap voltage or to match the full-scale reference among a system of KAD2708C chips. One option in the latter configuration is to use one KAD2708C's internally generated reference as the external reference voltage for the other chips in the system. Additionally, an externally provided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range. To select whether the full-scale reference is internally generated or externally provided, the digital input port VREFSEL should be set appropriately, low for internal or high for external.This pin also has an internal 18k pull-up resistor. To use the internally generated reference, VREFSEL can be tied directly to AVSS, and to use an external reference, VREFSEL can be left unconnected.
Reset
Recalibration of the ADC can be initiated at any time by driving the RST pin low for a minimum of one clock cycle. An open-drain driver is recommended. The calibration sequence is initiated on the rising edge of RST, as shown in Figure 21. The over-range output (OR) is set high once RST is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it is important that the analog input be within the converter's full-scale range in order to observe the transition. If the input is in an over-range state the OR pin will stay high and it will not be possible to detect the end of the calibration cycle. While RST is low, the output clock (CLKOUT) stops toggling and is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RST is deasserted. At 275MSPS the nominal calibration time is ~240ms.
CLKN CLKP Calibration Time RST Calibration Begins OR Calibration Complete CLKOUT
Analog Input
The fully differential ADC input (INP/INN) connects to the sample and hold circuit. The ideal full-scale input voltage is 1.5VPP, centered at the VCM voltage of 0.86V as shown in Figure 22.
V 1.8 1.4 1.0 0.6 -0.75V 0.2 t 0.75V INP INN VCM 0.86V
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven differentially in an ac-coupled configuration. The common-mode output voltage, VCM, should be used to properly bias each input as shown in Figures 23 and 24. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. The recommended biasing is shown in Figures 23 and 24.
FIGURE 21. CALIBRATION TIMING
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FN6812.0 December 5, 2008
KAD2708C
Clock Input
0.01F Analog In
ADT1-1WT ADT1-1WT
50O
KAD2708
VCM
0.1F
The clock input circuit is a differential pair (see Figure 29). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. The recommended drive circuit is shown in Figure 26. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance.
1kO
AVDD2 1nF CLKP 1nF 200O CLKN
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
1kO
ADTL1-12 Analog Input 1nF
ADTL1-12
25O
KAD2708
Clock Input TC4-1W
1nF
VCM
25O
0.1F
FIGURE 24. TRANSFORMER INPUT, HIGH IF APPLICATION
FIGURE 26. RECOMMENDED CLOCK DRIVE
A back-to-back transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of the input matched to VCM. The value of the termination resistor should be determined based on the desired impedance. The sample and hold circuit design uses a switched capacitor input stage, which creates current spikes when the sampling capacitance is reconnected to the input voltage. This creates a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance. A differential amplifier can be used in applications that require DC coupling, at the expense of reduced dynamic performance. In this configuration the amplifier will typically reduce the achievable SNR and distortion performance. A typical differential amplifier configuration is shown in Figure 25.
348O 69.8O
100O + Vin 0.22F
CM
Use of the clock divider is optional. The KAD2708C's ADC requires a clock with 50% duty cycle for optimum performance. If such a clock is not available, one option is to generate twice the desired sampling rate, then use the KAD2708C's divide-by-2 to generate a 50%-duty-cycle clock. This frequency divider uses the rising edge of the clock, so 50% clock duty cycle is assured. Table 2 describes the CLKDIV connection.
TABLE 2. CLKDIV PIN SETTINGS CLKDIV PIN AVSS AVDD DIVIDE RATIO 2 1
CLKDIV is internally pulled low, so a pull-up resistor or logic driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter and maximum SNR is shown in Equation 1 and is illustrated in Figure 27.
1 SNR = 20 log 10 ------------------- 2f t
IN J
25O
(EQ. 1)
151O
KAD2708
VCM
100O 49.9O 69.8O 348O
25O 0.1F
Where tJ is the RMS uncertainty in the sampling instant. This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as differential nonlinearity, aperture jitter and thermal noise.
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
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KAD2708C
10 0 95 90 85 tj=0.1 ps 14 Bits
SN R - dB
80 75 70 65 60 55 50 1 10 tj=1 00 ps tj=10 p s
tj=1 ps
12 Bits
Any internal aperture jitter combines with the input clock jitter, in a root-sum-square fashion since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR.
Digital Outputs
1 0 Bits
Data is output on a parallel bus with LVDS-compatible drivers.
1 00 0
1 00
In put Fr equen cy - MH z
The output format (Binary or Two's Complement) is selected via the 2SC pin as shown in Table 3.
TABLE 3. 2SC PIN SETTINGS 2SC PIN AVSS AVDD MODE Two's Complement Binary
FIGURE 27. SNR vs CLOCK JITTER
Equivalent Circuits
AVDD2
AVDD3 To Charge Pipeline
CLKP
INP 2pF
AVDD2
1 F
AVDD3
2 F
Csamp 0.3pF
To Clock Generation
INN 2pF
F1
2 F
Csamp 0.3pF
To Charge Pipeline
CLKN
AVDD2
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
OVDD OVDD
DATA
D[9:0]
FIGURE 30. LVCMOS OUTPUT
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KAD2708C Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02. Integral Non-Linearity (INL) is the deviation of each individual code from a line drawn from negative full-scale (1/2 LSB below the first code transition) through positive full-scale (1/2 LSB above the last code transition). The deviation of any given code from this line is measured from the center of that code. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N - 1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Its value in terms of input voltage is VFS/2. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the corresponding data. Power Supply Rejection Ratio (PSRR) is the ratio of a change in power supply voltage to the input voltage necessary to negate the resultant change in output code. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (SNR) (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component. The peak spurious spectral component may or may not be a harmonic. Two-Tone SFDR is the ratio of the RMS value of either input tone to the RMS value of the peak spurious component. The peak spurious component may or may not be an IMD product.
Clock Input Considerations
Use matched transmission lines to the inputs for the analog input and clock signals. Locate transformers, drivers and terminations as close to the chip as possible.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance. Avoid crossing ground and power-plane breaks with signal traces.
Unused Inputs
The RST and 2SC inputs are internally pulled up, and can be left open-circuit if not used. CLKDIV is internally pulled low, which divides the input clock by two. VREFSEL is internally pulled up. It must be held low for internal reference, but can be left open for external reference.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
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KAD2708C
Package Outline Drawing
L68.10x10B
68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/08
PIN 1 INDEX AREA 6 10.00
A B
4X 8.00 52 51 68 1
PIN 1 INDEX AREA 6 64X 0.50
10.00
Exp. DAP 7.70 Sq.
35 0.15 (4X) 34
TOP VIEW
17 18
68X 0.55
BOTTOM VIEW
68X 0.25
4
0.10 M C A B
0.90 Max 8.00 Sq
SEE DETAIL "X" C 0.10 C
64X 0.50
SIDE VIEW
0.08 C SEATING PLANE
68X 0.25 9.65 Sq
7.70 Sq
C
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. 68X 0.75
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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